1 ps8378b 08/09/99 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 product features ? very high-speed, low-noise universal bus driver with embedded resistor outputs ? meets pc133 sdram registered dimm specification ? implements output impedance control for low-noise and heavy-load applications ? fast propagation delay: 2.5ns max. for 50pf test load ?v cc = 3.3v or 2.5v or 1.8v ? packages available: ? 56-pin 240 mil wide plastic tssop (a) ? 56-pin 173 mil wide plastic tvsop (k) PI74AVC16834 18-bit universal bus driver with 3-state outputs product description pericom semiconductors pi74avc series of logic circuits are produced using the companys advanced 0.35 micron cmos technology, achieving industry leading speed. the 18-bit PI74AVC16834 universal bus driver is designed for 1.8v to 3.6v v cc operation. data flow from a to y is controlled by output enable (oe). the device operates in the transparent mode when le is low. the a data is latched if clk is held at a high or low logic level. if le is high, the a-bus is stored in the latch/flip-flop on the low-to-high transition of clk. when oe is high, the outputs are in the high- impedance state. the PI74AVC16834 bus driver is designed to drive an array of 133 mhz synchronous memory chips, with minimal undershoot/ overshoot noise, and to meet the input signal rise/fall time requirement of memory chips. the output drivers of this part have an embedded series-resistor. for dimm module design, no external series termination resistors near the buffer drivers or any other termination resistors are required. this feature simplifies dimm module layout design, and results in cost savings. product pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 25 26 27 28 32 31 30 29 oe clk y18 a18 gnd gnd y17 a17 y16 a16 v cc v cc y15 a15 y14 a14 y13 a13 gnd gnd y12 a12 y11 a11 y10 a10 y9 a9 y8 a8 y7 a7 gnd gnd y6 a6 y5 a5 y4 a4 v cc v cc y3 a3 y2 a2 y1 a1 gnd gnd nc nc nc gnd le gnd 56-pin a56 k56
2 ps8378b 08/09/99 PI74AVC16834 18-bit universal bus driver with 3-state outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 s t u p n i y s t u p t u o e oe lk l ca hxxx z llxl l llxh h lh - ll lh - hh lhhx o y ) 2 ( lhlx o y ) 3 ( pin name description oe output enable input (active low) le latch enable (active low) clk clock input a data input y data output gnd ground v cc power product pin description truth table (1) note: 1 h = high signal level l = low signal level z = high impedance - = transition low-to-high x = irrelevant 2. output level before the indicated steady-state input conditions were established, provided that clk is high before le goes high. 3. output level before the indicated steady-state input conditions were established. logic block diagram to 17 other channels clk le a1 54 28 30 oe 27 1d c1 clk y1 3
3 ps8378b 08/09/99 PI74AVC16834 18-bit universal bus driver with 3-state outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 storage temperature ............................................................................................................ . ?65c to +150c ambient temperature with power applied ............................................................................ ?40c to +85 c supply voltage range, v cc ............................................................................................................................... ................................................ ?0.5v to +4.6v input voltage range, v i (1) ............................................................................................................................... ..................................................... ?0.5v to +4.6v voltage range applied to any output in the high-impedance or power-off state, v o (1) ........... ?0.5v to +4.6v voltage range applied to any output in the high or low state, v o (1,2) ............................... ?0.5v to v cc +0.5v input clamp current, i ik (v i <0) ............................................................................................................. ?50ma output clamp current, i ok (v o <0) ........................................................................................................ ?50ma continuous output current, i o ................................................................................................................ 50ma continuous current through each v cc or gnd .................................................................................... 100ma package thermal impedance, q ja (3) : a (tssop) package .................................................................... 81c/w k (tvsop) package .................................................................... 86c/w note: 1. input and output negative voltage ratings may be exceeded if the input and output current ratings are observed. 2. output positive voltage rating may be exceeded up to 4.6v maximum if the output current rating is observed. 3. package thermal impedance is calculated in accordance with jesd 51. stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. maximum ratings (above which the useful life may be impaired. for user guidelines, not tested.)
4 ps8378b 08/09/99 PI74AVC16834 18-bit universal bus driver with 3-state outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 s r e t e m a r a pn o i t p i r c s e ds n o i t i d n o c t s e t. n i m. x a ms t i n u v c c e g a t l o v y l p p u s g n i t a r e p o5 6 . 16 . 3 v y l n o n o i t n e t e r a t a d2 . 1 v h i e g a t l o v t u p n i l e v e l - h g i h v c c v 2 . 1 =v c c v c c v 5 9 . 1 o t v 5 6 . 1 =v x 5 6 . 0 c c v c c v 7 . 2 o t v 3 . 2 =7 . 1 v c c v 6 . 3 o t v 3 =2 v l i e g a t l o v t u p n i l e v e l - w o l v c c v 2 . 1 =d n g v c c v 5 9 . 1 o t v 5 6 . 1 =v x 5 3 . 0 c c v c c v 7 . 2 o t v 3 . 2 =7 . 0 v c c v 6 . 3 o t v 3 =8 . 0 v n i e g a t l o v t u p n i06 . 3 v t u o e g a t l o v t u p t u o e t a t s e v i t c a0v cc e t a t s - 306 . 3 i s h o t n e r r u c t u p t u o l e v e l - h g i h ) 2 ( v c c v 5 9 . 1 o t v 5 6 . 1 =4 ? a m v c c v 7 . 2 o t v 3 . 2 =8 ? v c c v 6 . 3 o t v 3 =2 1 ? i s l o t n e r r u c t u p t u o l e v e l - w o l ) 2 ( v c c v 5 9 . 1 o t v 5 6 . 1 =4 v c c v 7 . 2 o t v 3 . 2 =8 v c c v 6 . 3 o t v 3 =2 1 d / t d v e t a r l l a f r o e s i r n o i t i s n a r t t u p n iv c c v 6 . 3 o t v 5 6 . 1 =5v / s n t a e r u t a r e p m e t r i a - e e r f g n i t a r e p o0 4 ?5 8c recommended operating conditions (1) note: 1. unused control inputs must be held high or low to prevent them from floating. 2. dynamic drive is greater than standard output drive of i oh = ?24ma and i ol = 24ma
5 ps8378b 08/09/99 PI74AVC16834 18-bit universal bus driver with 3-state outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 timing requirements over operating range dc electrical characteristics (over the operating range, t a = C40c to +85c, v cc = 3.3v 10%) notes: 1. for max. or min. conditions, use appropriate value specified under electrical characteristics for the applicable device typ e. 2. typical values are measured at +25c. 3. for i/o ports, the i oz includes the input leakage current. s r e t e m a r a ps n o i t i d n o c t s e tv c c ) 1 ( . n i m. p y t ) 2 ( . x a ms t i n u v h o i s h o 0 0 1 ? = m a v h i r ov l i 6 . 3 o t 5 6 . 1v c c -2 . 0 v i s h o 4 ? =ma v h i =v 7 0 . 15 6 . 12 . 1 i s h o 8 ? =ma v h i =v 7 . 13 . 25 7 . 1 i s h o 2 1 ? =ma v h i v 2 =0 . 33 . 2 v l o i s l o 0 0 1 = m av h i r ov l i 6 . 3 o t 5 6 . 12 . 0 i s l o =m 4a v l i =v 7 5 . 05 6 . 15 4 . 0 i s l o =m 8a v l i =v 7 . 03 . 25 5 . 0 i s l o =m 2 1a v l i =v 8 . 00 . 37 . 0 i i s t u p n i l o r t n o cv i =v c c d n g r o6 . 35 . 2 m a i f f o v i 0 =r ov 6 . 300 1 i z o ) 3 ( v o =v c c d n g r o= e ov c c 6 . 30 1 i c c v i =v c c d n g r oi o 0 =6 . 30 4 c i s t u p n i l o r t n o c v i =v c c d n g r o 5 . 25 . 4 f p 3 . 35 . 4 t u p n i a t a d 5 . 20 . 4 3 . 30 . 4 c o s t u p t u ov o =v c c d n g r o 5 . 25 . 6 3 . 35 . 6 s r e t e m a r a pn o i t p i r c s e d v c c v 8 . 1 = v 5 1 . 0 v c c v 5 . 2 = v 2 . 0 v c c v 3 . 3 = v 3 . 0 s t i n u . n i m. x a m. n i m. x a m. n i m. x a m f k c o l c y c n e u q e r f k c o l c0 5 10 5 10 5 1z h m t w e s l u p n o i t a r u d w o l e l0 . 22 . 10 . 1 s n w o l r o h g i h k l c0 . 22 . 10 . 1 t u s e m i t p u t e s k l c e r o f e b a t a d - 4 . 12 . 10 . 1 e l e r o f e b a t a d , - w o l r o h g i h k l c4 . 12 . 10 . 1 t h e m i t d l o h k l c r e t f a a t a d - 0 . 18 . 06 . 0 e l r e t f a a t a d - w o l r o h g i h k l c ,0 . 18 . 06 . 0
6 ps8378b 08/09/99 PI74AVC16834 18-bit universal bus driver with 3-state outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 switching characteristics over recommended operating free-air temperature range unless otherwise noted, see figures 1 through 3. note 1. load at 50pf and 500 w . r e t e m a r a p m o r f ) t u p n i ( o t ) t u p t u o ( v c c v 8 . 1 = v 5 1 . 0 v c c v 5 . 2 = v 2 . 0 v c c v 3 . 3 = ) 1 ( v 3 . 0 s t i n u . n i m. x a m. n i m. x a m. n i m. x a m f x a m 0 5 10 5 10 5 1z h m t d p a y 0 . 15 . 48 . 00 . 37 . 04 . 2 s n e l0 . 10 . 58 . 03 . 37 . 05 . 2 k l c0 . 15 . 48 . 00 . 37 . 05 . 2 t n e e o5 . 15 . 50 . 15 . 40 . 10 . 4 t s i d e o5 . 10 . 50 . 15 . 40 . 10 . 4 s r e t e m a r a p t s e t s n o i t i d n o c v c c v 8 . 1 =v c c v 5 . 2 =v c c v 3 . 3 = s t i n u . p y t. p y t. p y t c d p n o i t a p i s s i d r e w o p e c n a t i c a p a c d e l b a n e s t u p t u o c l , 0 = z h m 0 1 = f 5 48 42 5 f p d e l b a s i d s t u p t u o3 25 28 2 operating characteristics, t a = 25c
7 ps8378b 08/09/99 PI74AVC16834 18-bit universal bus driver with 3-state outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 c l =30pf (see note a) r 1 500 w from output under test gnd 2 x v cc open 1k w timing input data input v cc 0v v cc v cc /2 v cc /2 v cc /2 0v t su t h input t plh t plh output v cc /2 v cc v oh v ol 0v v cc /2 v cc /2 v cc /2 input v cc v cc /2 v cc /2 0v t w output control (low-level enabling) output waveform 2 s1 at gnd (see note b) t pzl t plz 0v v ol 0v output waveform 1 s1 at 2 x v ss (see note b) v oh C0.15v v ol +0.15v t phz t pzh v cc /2 v cc /2 v cc /2 v cc /2 v cc v cc v oh parameter measurement information (v cc = 1.8v 0.15v) t s e t1 s t d p t / z l p t l z p t / z h p t h z p n e p o v x 2 c c d n g load circuit voltage waveforms setup and hold times voltage waveforms propagation delay times voltage waveforms pulse duration voltage waveforms enable and disable times notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. all input pulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 w , t r 2ns, t r 2ns. d. the outputs are measured one at a time with one transition per measurement. e. t plz and t phz are the same as t dis . f. t pzl and t pzh are the same as t dis . g. t plh and t phl are the same as t dis . figure 1. load circuit and voltage waveforms
8 ps8378b 08/09/99 PI74AVC16834 18-bit universal bus driver with 3-state outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 parameter measurement information (v cc = 2.5v 0.2v) load circuit voltage waveforms setup and hold times voltage waveforms propagation delay times voltage waveforms pulse duration voltage waveforms enable and disable times notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. all input pulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 w , t r 2ns, t r 2ns. d. the outputs are measured one at a time with one transition per measurement. e. t plz and t phz are the same as t dis . f. t pzl and t pzh are the same as t dis . g. t plh and t phl are the same as t dis . figure 2. load circuit and voltage waveforms c l =30pf (see note a) 500 w from output under test gnd 2 x v cc open 500 w s 1 timing input data input v cc 0v v cc v cc /2 v cc /2 v cc /2 0v t su t h input t plh t plh output v cc /2 v cc v oh v ol 0v v cc /2 v cc /2 v cc /2 input v cc v cc /2 v cc /2 0v t w output control (low-level enabling) output waveform 2 s1 at gnd (see note b) t pzl t plz 0v v ol 0v output waveform 1 s1 at 2 x v ss (see note b) v oh C0.15v v ol +0.15v t phz t pzh v cc /2 v cc /2 v cc /2 v cc /2 v cc v cc v oh t s e t1 s t d p t / z l p t l z p t / z h p t h z p n e p o v x 2 c c d n g
9 ps8378b 08/09/99 PI74AVC16834 18-bit universal bus driver with 3-state outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 parameter measurement information (v cc = 3.3v 0.3v) load circuit voltage waveforms setup and hold times voltage waveforms propagation delay times voltage waveforms pulse duration voltage waveforms enable and disable times notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. all input pulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 w , t r 2ns, t r 2ns. d. the outputs are measured one at a time with one transition per measurement. e. t plz and t phz are the same as t dis . f. t pzl and t pzh are the same as t dis . g. t plh and t phl are the same as t dis . figure 3. load circuit and voltage waveforms c l =50pf (see note a) 500 w from output under test gnd 2 x v cc open 500 w s 1 timing input data input v cc 0v v cc v cc /2 v cc /2 v cc /2 0v t su t h input t plh t plh output v cc /2 v cc v oh v ol 0v v cc /2 v cc /2 v cc /2 input v cc v cc /2 v cc /2 0v t w output control (low-level enabling) output waveform 2 s1 at gnd (see note b) t pzl t plz 0v v ol 0v output waveform 1 s1 at 2 x v ss (see note b) v oh C0.3v v ol +0.3v t phz t pzh v cc /2 v cc /2 v cc /2 v cc /2 v cc v cc v oh t s e t1 s t d p t / z l p t l z p t / z h p t h z p n e p o v x 2 c c d n g pericom semiconductor corporation 2380 bering drive ? san jose, ca 95131 ? 1-800-435-2336 ? fax (408) 435-1100 ? http://www.pericom.com
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